1. Field
Exemplary embodiments of the present invention relate to semiconductor design technology, and more particularly, to boundary scan test technology of a semiconductor device.
2. Description of the Related Art
With high performance and high integration of semiconductor devices, the number of interface pins or balls for the semiconductor devices to exchange signals with the outside has increased. In general, a semiconductor device checks a connection state between an external input channel and an interface pin through a boundary scan test. That is, since interface pins are allocated to a plurality of external input channels, respectively, test data signals inputted through the plurality of input channels are transmitted through the interface pins. Then, the test data signals are buffered and latched in the semiconductor device and outputted to the outside through a boundary scan path to check the connection state between the input channels and the interface pins.
FIG. 1A is a block diagram and timing diagram illustrating an operation of a boundary capture test mode during a boundary scan test of a conventional semiconductor device.
FIG. 1B is a block diagram and timing diagram illustrating an operation of a boundary scan test mode during the boundary scan test of the conventional semiconductor device.
In general, the boundary scan test includes the boundary capture test mode of FIG. 1A and the boundary scan test mode of FIG. 1B.
Referring to FIG. 1A, in the boundary capture test mode when both of a scan test entry signal SENB and a capture test entry signal SSH are activated to a logic low level, a plurality of data DATA_0 to DATA_3 are applied in parallel from a system to the semiconductor device.
Referring to FIG. 1B, in the boundary scan test mode when the scan test entry signal SENB is activated to a logic low level and the capture test entry signal SSH is deactivated to a logic high level, the plurality of data DATA_0 to DATA_3 stored in the boundary capture test mode are sequentially transmitted through a boundary scan path and outputted to the outside of the semiconductor device through a scan data output channel.
FIG. 2 is a block diagram illustrating a circuit to perform a boundary scan test in the conventional semiconductor device.
Referring to FIG. 2, the circuit to perform a boundary scan test in the conventional semiconductor device includes a plurality of clock buffers 200<0>, 200<1>, . . . , a plurality of latches 220<0>, 220<1>, . . . , and a plurality of data buffers 210<0>, 210<1>, . . . . The plurality of clock buffers 200<0>, 200<1>, . . . are configured to receive and buffer a boundary test clock signal SCK in the boundary scan test mode. The plurality of latches 210<0>, 210<1>, . . . are configured to receive and store a plurality of data DATA_0, DATA_1, . . . in parallel in the boundary capture test mode, and form a boundary scan path to sequentially output the plurality of stored data . . . , SDATA_1, and SDATA_0 in the boundary scan test mode. The operations of the latches 210<0>, 210<1>, . . . are controlled in response to an output clock signal iSCK of the clock buffers 200<0>, 200<1>, . . . . The plurality of data buffers 210<0>, 210<1>, . . . are configured to buffer the plurality of data DATA_0, DATA_1, . . . , respectively.
FIG. 3 is a timing diagram illustrating an operation of the circuit performing a boundary scan test in the conventional semiconductor device shown in FIG. 2.
Referring to FIG. 3, the circuit to perform a boundary scan test in the conventional semiconductor device sequentially outputs a plurality of data DATA_1, DATA_2, . . . , DATA_K, DATA_K+1, and DATA_K+2 through the scan data output channel at the respective rising edges of the buffered boundary test clock signal iSCK in a state that the scan test entry signal SENB is activated to a logic low level and the capture test entry signal SSH is deactivated to a logic high level.
When the scan test entry signal SENB transitions from the activation state at a logic low level to the deactivation state at a logic high level, the boundary scan test mode ends. Data outputting through the scan data output channel, among the plurality of data DATA_1, DATA_2, . . . , DATA_K, DATA_K+1, and DATA_K+2 sequentially outputted, is maintained in a holding state.
Then, when the scan test entry signal SENB transitions from the deactivation state at a logic high level to the activation state at a logic low level, the boundary scan test mode starts again. The holding state of the outputting data ends, and next data are successively outputted at the respective rising edges of the buffered boundary test clock iSCK.
That is, the plurality of data DATA_1, DATA_2, DATA_1, DATA_2, . . . , DATA_K, DATA_K+1, and DATA_K+2 stored in the plurality of latches 220<0>, 220<1>, . . . , respectively, are outputted through the scan data output channel, based on the logic level of the scan test entry signal SENB.
Here, when the scan test entry signal SENB transitions from the deactivation state at a logic high level to the activation state at a logic low level in the deactivation period of the boundary test clock signal SCK (A), the holding state of the outputting data, e.g., DATA_K, is maintained during the deactivation period the boundary test clock signal SCK (A). The next data, e.g., DATA_K+2, may be outputted at the next rising edge of the buffered boundary test clock signal iSCK without any error.
However, when the scan test entry signal SENB transitions from the deactivation state at a logic high level to the activation state at a logic low level in the activation period of the boundary test clock signal SCK (B), the buffered boundary test clock signal iSCK is unexpectedly toggled by the activated boundary test clock signal SCK right after the scan test entry signal SENB transitions to the activation state. The holding state of the outputting data DATA_K suddenly ceases in response to the unexpected toggling, and the next data DATA_K+1 is outputted. That is, although the scan test entry signal SENB is toggled to delay the time point when the data DATA_K+1 is outputted through the scan data output channel for certain reasons, the data DATA_K+1 may be outputted earlier than a set time as the toggling is completed at the end of the activation period of the boundary test clock signal SCK. For reference, the reasons may indicate the conditions of various operations for the semiconductor device to be used as products.